Utilization of energy absorbing layer to improve metal flow and fill in a novel interconnect structure

ABSTRACT

Disclosed is a method for manufacturing an interconnect structure situated on a semiconductor wafer having a substrate assembly thereon. The interconnect structure is formed in a recess such as a trench, a hole, a via, or a combination of a trench and a hole or via within a dielectric material situated on the substrate assembly of the semiconductor wafer. At least one barrier layer is deposited within the recess. A seed layer helping to promote nucleation, deposition, and growth of a material that will be used to fill up the recess is then deposited on the barrier layer. An electrically conductive layer is then formed upon the seed layer. An energy absorbing layer will then be formed upon the conductor layer, where the energy absorbing layer has a greater thermal absorption capacity than that of the electrically conductive layer. The energy absorbing layer is heated, with or without an applied heightened pressure, to cause the conductor layer to flow so as to fill voids that have formed within the dielectric structure. Following the steps of heating or heating and pressurizing the energy absorbing layer, both the energy absorbing layer and a portion of the conductive layer situated above the dielectric structure are removed.

BACKGROUND OF THE INVENTION

[0001] 1. The Field of the Invention

[0002] The present invention relates to a metallized integrated circuitstructure, and particularly to a metallized interconnect structuresituated on a semiconductor substrate assembly and methods for making.

[0003] 2. The Relevant Technology

[0004] Current technology for metallization of an integrated circuitinvolves the forming of a conductive layer over the integrated circuit.A typical metallization process is one that is performed at the “backend of the line” which is after the formation of integrated circuitsthat are to be wired by the metallization process. A single conductivelayer is often formed so that it is situated above the integratedcircuit to be wired. After the conductive layer is formed, it is thenpatterned and etched into a shape of the desired wiring necessary tometallize the integrated circuit. Since the conductive layer is situatedabove the integrated circuit, the resultant metallization will also beabove the integrated circuit in a “wiring up” scheme.

[0005] Another type of metallization involves the formation of aconductive layer at least in part below the integrated circuit in arecess composed of an electrically insulative or dielectric material.Such a wiring scheme may be described as a “wiring down” scheme. Therecess can be either a trench, a hole, or a via. Depending upon theaspect ratio of the recess, poor step coverage of the conductive layerwithin the recess may result. Voids in the conductive layer within therecess may also result when the conductive layer does not completelyfill up the recess. Voids and poor step coverage can cause theintegrated circuit to experience an electrical failure. The electricalfailure can be experienced during fabrication of the integrated circuitor after a period of time that the integrated circuit has been in use,such as where electrical contact with the conductive layer in the recesshas been lost because the material of the conductive layer moves.

[0006] It would be an advantage in the art to overcome the problems ofpoor step coverage and voids.

SUMMARY OF THE INVENTION

[0007] In accordance with the invention as embodied and broadlydescribed herein, the present invention relates to the method formanufacturing an interconnect structure situated on a semiconductorwafer having a substrate assembly thereon. A novel interconnectstructure is also disclosed. The term substrate assembly is intendedherein to mean a substrate having one or more layers or structuresformed thereon. As such, the substrate assembly may be, by way ofexample and not by way of limitation, a doped silicon semiconductorsubstrate typical of a semiconductor wafer.

[0008] The interconnect structure is formed in a dielectric materialsituated on the substrate assembly of the semiconductor wafer. The novelprocess forms the dielectric material into a recess having a specifiedgeometry shape. The shape formed in the dielectric material willpreferably be a recess therein. The recess can be a trench, a hole, avia, or a combination of a trench and a hole or via. The dielectricshape can be formed by processing the dielectric material by way of dryetching or other recess-creating process.

[0009] Following the creation of the dielectric structure in thedielectric material, at least one diffusion barrier layer is formed overthe dielectric structure. The diffusion barrier layer is at leastpartially conformably formed upon the dielectric structure. The materialfrom which the diffusion barrier layer is substantially composed ispreferably selected from the group consisting of ceramics, metallics,and intermetallics. More preferably, the diffusion barrier layer issubstantially composed of a material that is selected from the groupconsisting of aluminum nitride, tungsten nitride, titanium nitride, andtantalum nitride

[0010] A seed layer is then formed upon the diffusion barrier layer. Theseed layer helps to promote nucleation, deposition, and growth of amaterial that will be used to fill up the dielectric structure. The seedlayer can also serve the purpose of increasing surface mobility of thebarrier layer which helps to make a desirable filling of the dielectricstructure in the metallization process. Preferably, the material fromwhich the seed layer is substantially composed is selected from thegroup consisting of ceramics, metallics, and intermetallics. Morepreferably, the material from which the seed layer is composed isselected from the group consisting of aluminum, titanium nitride,titanium, and titanium aluminide. Additionally and by comparison, thediffusion barrier layer will preferably be composed of a material havinga melting point greater than or equal to that of the material from whichthe seed layer is composed

[0011] An electrically conductive layer is then formed upon the seedlayer. The electrically conductive layer is the current carrier forelectrical signals that will communicate with an integrated circuitassociated therewith. Preferably, the electrically conductive layer issubstantially composed of aluminum or copper. The material from whichthe diffusion barrier layer is composed will preferably have a meltingpoint greater than that of a material from which the electricallyconductive layer is composed. The material from which the seed layer iscomposed will preferably have a melting point greater than or equal tothat of the material from which the electrically conductive layer iscomposed.

[0012] An energy absorbing layer is then formed upon the conductorlayer. The energy absorbing layer will preferably have a greater thermalabsorption capacity than that of the electrically conductive layer.Alternatively, the energy absorbing layer will preferably being composedof a material having a higher melting point than that of the materialfrom which the electrically conductive layer is composed. As anotheralternative, the energy absorbing layer will preferably be composed of amaterial having both a higher thermal insulation capacity and electricinsulation capacity than that of the material from which theelectrically conductive layer is composed.

[0013] The energy absorbing layer is heated to cause the conductor layerto flow so as to fill voids that have formed within the dielectricstructure. In conjunction with the heating of the energy absorbinglayer, a pressure above atmospheric pressure can be applied to thesemiconductor substrate assembly to better assist the process of causingthe conductor layer to flow so as to fill voids within the dielectricstructure. Preferably, the energy absorbing layer is substantiallycomposed of a material selected from the group consisting of titanium,titanium nitride, tungsten, tungsten nitride, silicon nitride, silicondioxide, tantalum, tantalum nitride, and carbon.

[0014] Following the steps of heating or heating and pressurizing theenergy absorbing layer, the energy absorbing layer is removed,preferably by planarizing. The planarizing step may also remove aportion of the conductive layer situated above the dielectric structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] A more particular description of the invention briefly describedabove will be rendered by reference to specific embodiments thereofwhich are illustrated in the appended drawings. Understanding that thesedrawings depict only typical embodiments of the invention and are nottherefore to be considered to be limiting of its scope, the inventionwill be described and explained with additional specificity and detailthrough the use of the accompanying drawings in which:

[0016]FIG. 1 is a partial cross-sectional elevation and perspective viewof a dielectric material that is situated upon a monocrystalline siliconlayer of a semiconductor wafer, the dielectric material having adielectric structure formed therein that is shaped as a recess in thedielectric material, the recess featuring the combination of a holeextending to a trench in the dielectric material, the hole terminatingat the monocrystalline silicon layer of the semiconductor wafer.

[0017]FIG. 2 is a partial perspective cross-sectional elevation view ofa portion of FIG. 1, showing various interconnect structure, including atrench in the dielectric material, a hole in the dielectric material,and a combination thereof, each said interconnect structure havingthereon one or more layers of each of a barrier layer, a seed layer, aconductive layer, and an energy absorbing layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018]FIG. 1 depicts a semiconductor substrate assembly 10. A lowersubstrate known as a silicon layer 22 is formed in semiconductorsubstrate assembly 10, and a dielectric material 14 is upon siliconlayer 22. Lower substrate or silicon layer 22 defines a plane andcomprises material selected from the group consisting of silicondioxide, silicate glass and mixtures or derivatives thereof. A hole 18having a cylindrical shape extends from silicon layer 22 to terminate ata trench 20 formed in dielectric material 14. Trench 20 is rectangularin cross-section.

[0019]FIG. 2 shows a cross-section 12 seen FIG. 1. Another trench 32,and another hole 34 are also depicted. Trench 32 is not situated over ahole as is trench 20. FIG. 2 also depicts a hole 34 having a triangularcross-section and extending from a top surface of dielectric material 14to terminate at silicon layer 22. When filed with materials for ametallization process and subsequently planarized, holes 18, 34, andtrenches 20, 32 become interconnect structures in the metallizationprocess as described below.

[0020] To initiate the metallization process, dielectric material 14 isformed upon silicon layer 22 by conventional processing, such asdepositing doped or undoped oxide by various CVD processes, or by TEOSdeposition. Next, dielectric material 14 has recesses formed therein,including for example holes 18, 34, and trenches 20, 32, the formationof which is by conventional processing methods such as patterning andetching.

[0021] After dielectric material 14 has been processed into the desiredconfiguration of recesses, the next step is to form a barrier layer 24over the dielectric structure 16. Barrier layer 24 may be formed, by wayof example and not by way of limitation, by multiple deposition of amaterial. The material from which barrier layer 24 is composedpreferably will act as an adhesion layer for materials formed thereon,and also will acts as a diffusion barrier to prevent the diffusion ofmaterial through barrier layer 24.

[0022] Barrier layer 24 will preferably be a substantially continuouscoating of material over the recesses in dielectric material 14. Barrierlayer 24 may be comprised of refractory metals or nitrides thereof, suchas titanium, tungsten, tantalum, titanium nitride, tungsten nitride, ortantalum nitride. Typically, barrier layer 24 is titanium and/ortitanium nitride together. Barrier layer 24 can be particularlyimportant in the areas where holes 18, 34 extend past dielectricmaterial 14 to terminate at silicon layer 22.

[0023] The next step, which may be desirable in the inventive methoddepending upon the composition of materials used to fill the recesses indielectric material 14, is to thermally process barrier layer 24. Thethermal processing of barrier layer 24 helps to improve electricalcontact of the interconnect structures being formed. For example, iftitanium is deposited, then it is desirable that a thermal process beperformed. The thermal process would preferably be heating thesemiconductor substrate assembly in a nitrogen environment at a selectedtemperature at which nitrides are formed on the surface of the titanium.If barrier layer 24 comprises titanium or titanium nitride, argon may beused as the environment for thermal processing. In this example,titanium exposed to the nitrogen environment would form titanium nitrideand exposed silicon would form silicon nitride. As the thermal processheats the semiconductor substrate assembly, titanium silicide would formso as to create a desirable contact resistance with silicon layer 22.

[0024] A seed layer 26 is formed over barrier layer 24 in the next stepof the inventive method. The type of material used as seed layer 26 isdependant upon subsequent processing. If some type of subsequent reflowprocess is needed for later added layers, or even a CVD process is goingto be used for the formation of seed layer 26, seed layer 26 willpreferably be formed prior to subsequent processing so as to cleanbarrier layer 24. The use of seed layer 26 provides a surface on barrierlayer 24 that is substantially free of contaminates that may interferewith surface diffusion. Seed layer 26 promotes the deposition and growthof a layer of material that will be formed thereon. Additionally, seedlayer 26 will preferably be the main conductor for current in theinterconnect structure and will promote surface mobility of materialsformed thereon so as to fill the recesses in dielectric material 14 is adesirable manner.

[0025] By way of example of materials and processes for formation ofseed layer 26, a CVD tungsten process can be used. When so processedthere will be a nucleation of seed layer 26 that will be rich in bothsilicon and hydrogen, initially. The CVD tungsten process will thenpreferably undergo a chemistry change in the middle thereof so as tobecome rich in hexflouride such that a more pure form of tungstenmaterial makes up seed layer 26. Those of ordinary skill in the art willunderstand the selection of proper seed layer 26 compositions, whichselection may be done empirically utilizing chemical potentialdifferences and differences in diffusion characteristics of materials.

[0026] The seed layer may also be made of titanium nitride, which ispreferred when aluminum is used in the interconnect structures. If so,the seed layer should be deposited in situ prior to filling theinterconnect structures with aluminum so as to enable the aluminum tofreely flow and to avoid binding up the flow of the aluminum. Multiplelayers can be used to make up the seed layer, which multiple layers willpreferably be deposited in a vacuum system and will be composed, forexample, of both titanium nitride and/or silicon.

[0027] The next step in the inventive method is the formation of aconductor layer 28. Conductor layer 28 will preferably be composed oftypical metallization conductor materials. For example, if a reflow or afill process with aluminum process is going to be used, then an aluminumand high pressure fill would be used to substantially cover seed layer26 in the recesses within dielectric material 14. The composition ofconductor layer 28 may depend on the aspect ratio of the recesses withindielectric material 14. Aspect ratios below four (4) may not require ahigh pressure fill of the recesses. Another example of a conductormaterial is copper.

[0028] When aluminum is used as conductor layer 28, the composition ofbarrier layer 24 will preferably be selected to avoid a heat inducedreaction of aluminum with silicon in silicon layer 22 so as to formtetrahedrons in the silicon, wherein by a detrimental effect isrealized.

[0029] An energy absorbing layer 30 is then formed, preferably bydeposition, upon conductor layer 28. Energy absorbing layer 30 retainsthermal energy and comprises a material that has a higher thermalconductivity than conductor layer 28. By way of example and notlimitation, if conductor layer 28 is composed of aluminum and energyabsorbing layer 30 is composed of tungsten, the tungsten has a highermelting point that aluminum. This results in the tungsten retaining moreenergy.

[0030] From a spectral point of view, if aluminum is used as conductorlayer 28 and depending how the aluminum layer is deposited, it ispossible to obtain something that is not as spectrally reflective. Apreferable characteristic of energy absorbing layer 30 is that it mustbe able to absorb more energy than the material that is used asconductor layer 28. The purpose behind this requirement is that whenchallenging structures (e.g. recesses in dielectric material 14 havingaspect ratios greater than four (4) to one (1) are being formed whichare to be filled with a conductor, the conductor will flow more freelyto fill a recess when thermal energy is retained within the conductor bya layer thereon that will better retain such thermal energy. As such,the flowablility of the conductor is enhanced so that diffusion thereofinto the recess is bettered.

[0031] Enhancing the diffusion characteristics of the material of theconductor is achieved by either volume diffusion or surface diffusion,each of which are time and temperature dependent. The temperature of theconductor is held high for at a longer period of time while underlyingor overlying materials retain thermal energy. The formation of energyabsorbing layer 30 on conductor layer 28 substantially retains thermalenergy under an interfacial surface of energy absorbing layer 30 so thatthe thermal energy can diffuse into conductor layer 28.

[0032] By way of example, if conductor layer 28 is aluminum, energyabsorbing layer 30 can be titanium nitride, tungsten, or even adielectric substance. A layer of titanium nitride is less thermallyconductive than aluminum. If conductor layer 28 is copper, examples ofenergy absorbing layers 30 are tungsten, titanium nitride, tantalum orcarbon.

[0033] The next step of the inventive method is to apply energy toenergy absorbing layer 30. The energy that is applied to energyabsorbing layer 30 is transmitted to conductor layer 28. Conductor layer28 is then able to flow and fill voids that have formed in recesseswithin dielectric material 14. With the voids removed, desirable stepcoverage of the recesses within dielectric material 14, and desirablefill of the recesses is achieved. Examples of ways to apply energy toenergy absorbing layer 30 include, but are not limited to, lasers, tubefurnaces, RTP or other kinds of radiant or thermal energy. Preferably,energy absorbing layer 30 will be heated.

[0034] A preferable step that follows the forgoing steps is the removalof materials from the semiconductor substrate assembly by an abrasiveplanarizing process, for example, chemical mechanical planarizing.Material will be removed during the planarizing process untilplanarization line 36 seen in FIG. 2 is reached. The resultinginterconnect structures have been metallized so as to be buried withindielectric material 14, and as such can be considered to be ametallization by “wire-down” technology. Subsequent and conventionalprocessing can then following in the fabrication processing of thesemiconductor substrate assembly.

[0035]FIG. 2 shows a novel dual damescene structure depicted as hole 18and trench 20 filled with each of barrier layer 24, seed layer 26, andconductor layer 28, where trench 20 has been planarized at planarizationline 36. Planarization line 36 makes the metallization in an “inlaid”form. The two or “dual” metallization damescene structure is seen in theinlaid combination of both hole 18 and trench 20.

[0036] The disclosed novel method is capable of desirable step coverageand being capable of filling in a recess within a dielectric materialhaving an aspect ratio greater than about four (4) to one (1). As such,the novel process improves both the yield and reliability overconventional processes.

[0037] The present invention may be embodied in other specific formswithout departing from its spirit or essential characteristics. Thedescribed embodiments are to be considered in all respects only asillustrated and not restrictive. The scope of the invention is,therefore, indicated by the appended claims rather than by the foregoingdescription. All changes which come within the meaning and range ofequivalency of the claims are to be embraced within their scope.

What is claimed and desired to be secured by United States LettersPatent is:
 1. A method for manufacturing an interconnect structurecomprising the steps of: forming a recess within a dielectric materialsituated on a semiconductor lower substrate, said recess extending belowa top surface of said dielectric material; forming a diffusion barrierlayer on the recess within the dielectric material; forming a seed layeron the diffusion barrier layer, the diffusion barrier layer beingcomposed of a material having a melting point greater than or equal tothat of a material from which the seed layer is composed; forming anelectrically conductive layer on the seed layer, the material from whichthe diffusion barrier layer is composed having a melting point greaterthan that of a material from which the electrically conductive layer iscomposed, the material from which the seed layer is composed having amelting point greater than or equal to that of the material from whichthe electrically conductive layer is composed; forming an energyabsorbing layer on said electrically conductive layer, said energyabsorbing layer having a greater thermal absorption capacity than thatof said electrically conductive layer; applying energy to said energyabsorbing layer so to as heat said electrically conductive layer and tocause said electrically conductive layer to flow within said recess; andremoving portions of the energy absorbing layer and the electricallyconductive layer that are situated above the top surface of thedielectric material.
 2. A method for manufacturing an interconnectstructure as recited in claim 1 , wherein the step of forming adiffusion barrier layer on the recess within the dielectric material isa CVD deposition step.
 3. A method for manufacturing an interconnectstructure as recited in claim 1 , wherein the material from which thediffusion barrier layer is substantially composed is selected from thegroup consisting of ceramics, metallics, and intermetallics.
 4. A methodfor manufacturing an interconnect structure as recited in claim 1 ,wherein the material from which the diffusion barrier layer is composedis selected from the group consisting of aluminum nitride, tungstennitride, titanium nitride, and tantalum nitride.
 5. A method formanufacturing an interconnect structure as recited in claim 1 , furthercomprising the step, prior to the step of forming a seed layer on thediffusion barrier layer, of heating the diffusion barrier layer is anenvironment substantially containing a nitrogen gas.
 6. A method formanufacturing an interconnect structure as recited in claim 1 , whereinthe step of depositing a seed layer on the diffusion barrier layer is aCVD deposition step.
 7. A method for manufacturing an interconnectstructure as recited in claim 1 , wherein the material from which theseed layer is substantially composed is selected from the groupconsisting of ceramics, metallics, and intermetallics.
 8. A method formanufacturing an interconnect structure as recited in claim 1 , whereinthe material from which the seed layer is composed is selected from thegroup consisting of aluminum, titanium nitride, titanium, and titaniumaluminide.
 9. A method for manufacturing an interconnect structure asrecited in claim 1 , wherein the material from which the electricallyconductive layer is composed is selected from the group consisting ofaluminum and copper.
 10. A method for manufacturing an interconnectstructure as recited in claim 1 , wherein the energy absorbing layer issubstantially composed of a material selected from the group consistingof titanium, titanium nitride, tungsten, tungsten nitride, siliconnitride, silicon dioxide, tantalum, tantalum nitride, and carbon.
 11. Amethod for manufacturing an interconnect structure as recited in claim 1, wherein the step of applying energy to said energy absorbing layer toheat the energy absorbing layer utilizes at least one energy sourceselected from the group consisting of a laser, a furnace, and an RTPlamp.
 12. A method for manufacturing an interconnect structure asrecited in claim 1 , wherein said step of removing portions of theenergy absorbing layer and the electrically conductive layer is anabrasive planarization step.
 13. A method for manufacturing aninterconnect structure as recited in claim 12 , wherein said step ofremoving portions of the energy absorbing layer and the electricallyconductive layer is a chemical mechanical planarizing step.
 14. A methodfor manufacturing an interconnect structure as recited in claim 1 ,wherein the recess has an aspect ratio greater than about four (4) toone (1).
 15. A method for manufacturing an interconnect structure asrecited in claim 1 , wherein the recess comprises a contact holesituated below a trench, said semiconductor substrate assembly having alower substrate defining a plane, said contact hole terminating at anend thereof at said lower substrate and terminating at an opposite endthereof at said trench, said trench extending from said opposite end ofsaid contact hole to a top surface of said dielectric material, thetrench extending substantially parallel to the plane of the lowersubstrate.
 16. A method for manufacturing an interconnect structurecomprising the steps of: patterning and etching a dielectric materialsituated on a semiconductor substrate assembly so as to form a recesswithin the dielectric material, said recess being situated below a topsurface of said dielectric material; depositing a diffusion barrierlayer within the recess within the dielectric material, the diffusionbarrier layer being composed of a material selected from the groupconsisting of ceramics, metallics, and intermetallics; depositing a seedlayer on the diffusion barrier layer, the seed layer being composed of amaterial selected from the group consisting of ceramics, metallics, andintermetallics, the material from which the diffusion barrier layer iscomposed having a melting point greater than or equal to that of thematerial from which the seed layer is composed; depositing anelectrically conductive layer on the seed layer, the material from whichthe diffusion barrier layer is composed having a melting point greaterthan that of the material from which the electrically conductive layeris composed, the material from which the seed layer is composed having amelting point greater than or equal to that of the material from whichthe electrically conductive layer is composed; depositing an energyabsorbing layer on said electrically conductive layer, said energyabsorbing layer being composed of a material having a higher meltingpoint than that of the material from which the electrically conductivelayer is composed; heating the energy absorbing layer so to as heat theconductive layer and to cause said conductive layer to flow within saidrecess; and planarizing the semiconductor substrate assembly so as toremove those portions of the energy absorbing layer and the electricallyconductive layer that are situated above the top surface of thedielectric material.
 17. A method for manufacturing an interconnectstructure as recited in claim 16 , wherein the material from which thediffusion barrier layer is composed is selected from the groupconsisting of aluminum nitride, tungsten nitride, titanium nitride, andtantalum nitride.
 18. A method for manufacturing an interconnectstructure as recited in claim 16 , wherein the material from which theseed layer is composed is selected from the group consisting ofaluminum, titanium nitride, titanium, and titanium aluminide.
 19. Amethod for manufacturing an interconnect structure as recited in claim16 , wherein the material from which the electrically conductive layeris composed is selected from the group consisting of aluminum andcopper.
 20. A method for manufacturing an interconnect structure asrecited in claim 16 , wherein the energy absorbing layer issubstantially composed of a material selected from the group consistingof titanium, titanium nitride, tungsten, tungsten nitride, siliconnitride, silicon dioxide, tantalum, tantalum nitride, and carbon.
 21. Amethod for manufacturing an interconnect structure as recited in claim16 , wherein the recess has an aspect ratio greater than about 4 to 1.22. A method for manufacturing an interconnect structure as recited inclaim 16 , wherein the recess comprises a contact hole situated below atrench, said semiconductor substrate assembly having a lower substratedefining a plane, said contact hole terminating at an end thereof atsaid lower substrate and terminating at an opposite end thereof at saidtrench, said trench extending from said opposite end of said contacthole to a top surface of said dielectric material, the trench extendingsubstantially parallel to the plane of the lower substrate.
 23. A methodfor manufacturing an interconnect structure comprising the steps of:patterning and etching a dielectric material situated on a semiconductorsubstrate assembly so as to form a recess within the dielectricmaterial, said recess being situated below a top surface of saiddielectric material; depositing a diffusion barrier layer within therecess within the dielectric material, the diffusion barrier layer beingcomposed of a material selected from the group consisting of aluminumnitride, tungsten nitride, titanium nitride, and tantalum nitride;depositing a seed layer on the diffusion barrier layer, the seed layerbeing composed of a material selected from the group consisting ofaluminum, titanium nitride, titanium, and titanium aluminide, thematerial from which the diffusion barrier layer is composed having amelting point greater than or equal to that of the material from whichthe seed layer is composed; depositing an electrically conductive layeron the seed layer, the material from which the diffusion barrier layeris composed having a melting point greater than that of a material fromwhich the electrically conductive layer is composed, the material fromwhich the seed layer is composed having a melting point greater than orequal to that of the material from which the electrically conductivelayer is composed, the material from which the electrically conductivelayer is composed is selected from the group consisting of aluminum andcopper; depositing an energy absorbing layer on said electricallyconductive layer, said energy absorbing layer being composed of amaterial having a higher melting point than that of the material fromwhich the electrically conductive layer is composed, the energyabsorbing layer being is substantially composed of a material selectedfrom the group consisting of titanium, titanium nitride, tungsten,tungsten nitride, silicon nitride, silicon dioxide, tantalum, tantalumnitride, and carbon; heating the energy absorbing layer so to as heatthe conductive layer and to cause said conductive layer to flow withinsaid recess; and planarizing the semiconductor substrate assembly so asto remove those portions of the energy absorbing layer and theelectrically conductive layer that are situated above the top surface ofthe dielectric material.
 24. A method for manufacturing an interconnectstructure comprising the steps of: forming a dielectric material on amonocrystalline silicon layer of a semiconductor substrate assembly,said monocrystalline silicon layer defining a plane; patterning andetching the dielectric material so as to form a recess within saiddielectric material, said recess comprising a contact hole situatedbelow a trench, said contact hole terminating at an end thereof at thesilicon layer and terminating at an opposite end thereof at said trench,said trench extending from said opposite end of said contact hole to atop surface of said dielectric material, the trench being substantiallyparallel to the plane of the monocrystalline silicon layer; depositing adiffusion barrier layer within the recess within the dielectricmaterial, the diffusion barrier layer being composed of a materialselected from the group consisting of ceramics, metallics, andintermetallics; depositing a seed layer on the diffusion barrier layer,the seed layer being composed of a material selected from the groupconsisting of ceramics, metallics, and intermetallics, the material fromwhich the diffusion barrier layer is composed having a melting pointgreater than or equal to that of the material from which the seed layeris composed; depositing a layer substantially composed of aluminum onthe seed layer, the material from which the diffusion barrier layer iscomposed having a melting point greater than that of aluminum, thematerial from which the seed layer is composed having a melting pointgreater than or equal to that of aluminum; depositing an energyabsorbing layer on said electrically conductive layer, said energyabsorbing layer being composed of a material having both a higherthermal insulation capacity and electric insulation capacity than thatof the material from which the electrically conductive layer iscomposed; heating the energy absorbing layer so to as heat theconductive layer and to cause said conductive layer to flow within saidrecess; and planarizing the semiconductor substrate assembly so as toremove those portions of the energy absorbing layer and the electricallyconductive layer that are situated above the top surface of thedielectric material.
 25. A method for manufacturing an interconnectstructure as recited in claim 24 , wherein the material from which thediffusion barrier layer is composed is selected from the groupconsisting of aluminum nitride, tungsten nitride, titanium nitride, andtantalum nitride.
 26. A method for manufacturing an interconnectstructure as recited in claim 24 , wherein the material from which theseed layer is composed is selected from the group consisting ofaluminum, titanium nitride, titanium, and titanium aluminide.
 27. Amethod for manufacturing an interconnect structure as recited in claim24 , wherein the material from which the energy absorbing layer issubstantially composed is selected from the group consisting oftitanium, titanium nitride, tungsten, tungsten nitride, silicon nitride,silicon dioxide, tantalum, tantalum nitride, and carbon.
 28. A methodfor manufacturing an interconnect structure comprising the steps of:forming at least one silicon layer on a monocrystalline silicon layer ofa semiconductor substrate assembly, said silicon layer being selectedfrom the group consisting of undoped silicon dioxide, doped silicondioxide, undoped silicate glass, and doped silicate glass, wherein saidmonocrystalline silicon layer defines a plane; patterning and etchingthe at least one silicon dioxide layer so as to form a recess therein,said recess comprising a contact hole situated below a trench, saidcontact hole terminating at an end thereof at the at least one siliconlayer and terminating at an opposite end thereof at said trench, saidtrench extending from said opposite end of said contact hole to a topsurface of said at least one silicon layer, the trench beingsubstantially parallel to the plane of the monocrystalline siliconlayer; depositing a diffusion barrier layer within the recess within theat least one silicon layer, the diffusion barrier layer being composedof a material selected from the group consisting of aluminum nitride,tungsten nitride, titanium nitride, and tantalum nitride; depositing aseed layer on the diffusion barrier layer, the seed layer being composedof a material selected from the group consisting of aluminum, titaniumnitride, titanium, and titanium aluminide, the material from which thediffusion barrier layer is composed having a melting point greater thanor equal to that of the material from which the seed layer is composed;depositing a layer substantially composed of aluminum on the seed layer,the material from which the diffusion barrier layer is composed having amelting point greater than that of aluminum, the material from which theseed layer is composed having a melting point greater than or equal tothat of aluminum; depositing an energy absorbing layer on saidelectrically conductive layer, said energy absorbing layer beingcomposed of a material having both a higher thermal insulation capacityand electric insulation capacity than that of the material from whichthe electrically conductive layer is composed, the material from whichthe energy absorbing layer is substantially composed is selected fromthe group consisting of titanium, titanium nitride, tungsten, tungstennitride, silicon nitride, silicon dioxide, tantalum, tantalum nitride,and carbon; heating the energy absorbing layer so to as heat theconductive layer and to cause said conductive layer to flow within saidrecess; and planarizing the semiconductor substrate assembly so as toremove those portions of the energy absorbing layer and the electricallyconductive layer that are situated above the top surface of the at leastone silicon layer.
 29. An interconnect structure comprising: a lowersubstrate situated on a semiconductor substrate assembly, said lowersubstrate defining a plane; a dielectric material on the lower substratehaving a planar top surface; a recess within said dielectric material,said recess comprising a contact hole situated below a trench, saidcontact hole terminating at an end thereof at the lower substrate andterminating at an opposite end thereof at said trench, said contact holebeing oriented substantially perpendicular to the plane of said lowersubstrate, said trench extending from said opposite end of said contacthole to a top surface of said dielectric material, the trench extendingsubstantially parallel to the plane of said lower substrate; and anelectrically conductive layer situated within and filling both thecontact hole and the trench and extending to terminate at the planar topsurface of the dielectric material.
 30. An interconnect structurecomprising: a lower substrate situated on a semiconductor substrateassembly, said lower substrate defining a plane; a dielectric materialon the lower substrate having a planar top surface; a recess within saiddielectric material, said recess comprising a contact hole situatedbelow a trench, said contact hole terminating at an end thereof at thesilicon layer and terminating at an opposite end thereof at said trench,said contact hole being oriented substantially perpendicular to theplane of said lower substrate, said trench extending from said oppositeend of said contact hole to a top surface of said dielectric material,the trench extending substantially parallel to the plane said lowersubstrate; a diffusion barrier layer on the trench and the contact hole;a seed layer on the diffusion barrier layer, the diffusion barrier layerbeing composed of a material having a melting point greater than orequal to that of a material from which the seed layer is composed; andan electrically conductive layer on the seed layer and extending toterminate at the planar top surface of the dielectric material, thematerial from which the diffusion barrier layer is composed having amelting point greater than that of a material from which theelectrically conductive layer is composed, the material from which theseed layer is composed having a melting point greater than or equal tothat of the material from which the electrically conductive layer iscomposed.
 31. An interconnect structure as defined in claim 30 , whereinthe material from which the diffusion barrier layer is substantiallycomposed is selected from the group consisting of aluminum nitride,tungsten nitride, titanium nitride, and tantalum nitride.
 32. Aninterconnect structure as defined in claim 30 , wherein the materialfrom which the seed layer is substantially composed is selected from thegroup consisting of aluminum, titanium nitride, titanium, and titaniumaluminide.
 33. An interconnect structure as defined in claim 30 ,wherein the material from which the electrically conductive layer issubstantially composed is selected from the group consisting of aluminumand copper.
 34. An interconnect structure comprising: a monocrystallinesilicon layer of a semiconductor substrate assembly, saidmonocrystalline silicon layer defining a plane; a dielectric material onthe monocrystalline silicon layer; a recess within said dielectricmaterial, said recess comprising a contact hole situated below a trench,said contact hole terminating at an end thereof at the silicon layer andterminating at an opposite end thereof at said trench, said contact holebeing oriented substantially perpendicular to the plane of saidmonocrystalline silicon layer, said trench extending from said oppositeend of said contact hole to a top surface of said dielectric material,the trench extending substantially parallel to the plane of saidmonocrystalline silicon layer; a diffusion barrier layer on the trenchand the contact hole, the diffusion barrier layer being substantiallycomposed of a material selected from the group consisting of aluminumnitride, tungsten nitride, titanium nitride, and tantalum nitride; aseed layer on the diffusion barrier layer, the seed layer beingsubstantially composed of a material selected from the group consistingof aluminum, titanium nitride, titanium, and titanium aluminide, thematerial from which the diffusion barrier layer is composed having amelting point greater than or equal to that of the material from whichthe seed layer is composed; and an electrically conductive layer on theseed layer and extending to terminate at the planar surface of thedielectric material, the material from which the diffusion barrier layeris composed having a melting point greater than that of the materialfrom which the electrically conductive layer is composed, the materialfrom which the seed layer is composed having a melting point greaterthan or equal to that of the material from which the electricallyconductive layer is composed, the material from which the electricallyconductive layer is substantially composed being selected from the groupconsisting of aluminum and copper.
 35. An interconnect structure recitedin claim 34 , wherein the contact hole has an aspect ratio greater thanabout 4 to 1.